DC Field | Value | Language |
---|---|---|
dc.contributor.author | Karpovsky, Mark | en |
dc.contributor.author | Stanković, Radomir | en |
dc.contributor.author | Astola, Jaakko | en |
dc.date.accessioned | 2020-05-01T20:29:14Z | - |
dc.date.available | 2020-05-01T20:29:14Z | - |
dc.date.issued | 2004-01-01 | en |
dc.identifier.isbn | 978-0-7803-8251-X | - |
dc.identifier.issn | 0271-4310 | en |
dc.identifier.uri | http://researchrepository.mi.sanu.ac.rs/handle/123456789/2103 | - |
dc.description.abstract | In VLSI design, crossings of interconnections occupy space and cause delay. In particular, it is desirable to have planar networks for FPGA synthesis and sub-micron LSIs, since delays in the interconnections and crossings are comparable to the delays for logic circuits. Decision diagrams (DDs). provide a simple technology mapping, and planar DDs result in planar networks. In this paper, we present a deterministic method to construct planar Linearly Transformed Binary Decision Diagrams (BDDs) by Walsh transform spectral coefficients. | en |
dc.publisher | IEEE | - |
dc.relation.ispartof | Proceedings - IEEE International Symposium on Circuits and Systems | en |
dc.title | Construction of linearly transformed planar BDD by Walsh coefficients | en |
dc.type | Conference Paper | en |
dc.relation.conference | IEEE International Symposium on Circuits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004 | - |
dc.identifier.doi | 10.1109/ISCAS.2004.1329054 | - |
dc.identifier.scopus | 2-s2.0-4344688715 | en |
dc.relation.volume | 4 | en |
item.cerifentitytype | Publications | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.openairetype | Conference Paper | - |
item.grantfulltext | none | - |
item.fulltext | No Fulltext | - |
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